In general, a memory device generates and uses an internal voltage required for its internal operation using a power voltage (VDD) and a ground voltage (VSS) supplied from the outside. The voltage required for internal operation of the semiconductor memory device includes an internal power (VCORE) supplied to a memory core region, a high voltage (Vpp) used upon driving of a word line or overdriving and a back bias voltage (VBB) supplied as a bulk voltage of an NMOS transistor in the core region.
The internal voltage also includes a cell plate voltage (VCP) used as a plate voltage of a memory cell capacitor and a bit line precharge voltage (VBLP) used to precharge a bit line. In general, the cell plate voltage (VCP) and the bit line precharge voltage (VBLP) are generated from the internal power (VCORE) and generated to a half level of the internal power (VCORE) to minimize current consumption.
FIG. 1 is a circuit diagram illustrating a conventional internal voltage generation circuit.
The conventional internal voltage generation circuit, as illustrated in FIG. 1, for generating a cell plate voltage VCP or a bit line precharge voltage VBLP voltage-divides the internal power VCORE through resistance elements R10, R11 and drives the internal voltage VCP/VBLP by comparing a level of a voltage of a node nd10 generated to a half level of the internal power VCORE and a level of the internal voltage VCP/VBLP.
Operation of the internal voltage generation circuit shown in FIG. 1 will be described in more detail.
Since levels of pull-up driving signal PDRV and pull-down driving signal NDRV are also regularly maintained when the level of the internal voltage VCP/VBLP is not varied at the half level of the internal power VCORE, the internal voltage VCP/VBLP is driven by a regular current and is maintained at a regular level.
In this state, if the level of the internal voltage VCP/VBLP is lowered below the voltage of the node nd10, the levels of the pull-up driving signal PDRV and the pull-down driving signal NDRV are gradually decreased and a turn-on degree of a PMOS transistor P17 becomes larger than a turn-on degree of an NMOS transistor N19. Accordingly, the level of the internal voltage VCP/VBLP is increased. Also, if the level of the internal voltage VCP/VBLP is raised above the voltage of the node nd10, the levels of the pull-up driving signal PDRV and the pull-down driving signal NDRV are gradually increased and the turn-on degree of the NMOS transistor N19 becomes larger than the turn-on degree of the PMOS transistor P17. Accordingly, the level of the internal voltage VCP/VBLP is decreased. In other words, the internal voltage generation circuit controls the level of the internal voltage VCP/VBLP to be generated to a half level of the internal power VCORE.
In general, since the level of the internal voltage VCP/VBLP is maintained regularly when the semiconductor memory device is in a standby mode, the PMOS transistor P17 and the NMOS transistor N19 are turned off and are in a state of not driving the internal voltage VCP/VBLP. A period where a current for driving the internal voltage VCP/VBLP (hereinafter, referred to as ‘driving current’) does not flow at all through the PMOS transistor P17 and the NMOS transistor N19 as described above is referred to as a dead zone. Meanwhile, when the semiconductor memory device performs active operation, the level of the internal voltage VCP/VBLP varies significantly as consumption of the internal voltage VCP/VBLP is increased.
However, the PMOS transistor P17 and the NMOS transistor N19 have significantly large parasitic capacitances since the PMOS transistor P17 and the NMOS transistor N19 that drive the internal voltage VCP/VBLP are formed in a large size for the increase in the drivability. Such large value of the parasitic capacitance acts as a factor that lowers a response speed of the internal voltage generation circuit.